Thermal and free carrier laser interferometric mapping and failure analysis of anti-serial smart power ESD protection structures

摘要

Thermal and free carrier distribution during electrostatic discharge (ESD) - like stress arc investigated in anti- serial smart power technology ESD protection devices by using a laser interferometry mapping technique. The temperature- and free carrier - induced phase shift along the device length and width is studied as a function of stress current. Two positive phase peaks due to heat dissipation caused by a vertical and a lateral current path are found under the emitter contact and in the middle of the structure of an active npn transistor, respectively. A negative phase peak is found at the position of the forward biased pn junction of an inactive transistor, where a high carrier injection occurs. The positions of hot spots obtained from the thermal mapping method are correlated with the results of physical failure analysis using the infrared microscopy.