High reliability power VDMOS Transistors in Bipolar/CMOS/DMOS technology

摘要

This paper presents results of reliability investigation of power VDMOS FET in a Bipolar/CMOS/DMOS technology, encapsulated in hermetic ceramic package, obtained from high temperature gate stress (HTGS at 150℃ 1000h), high temperature reverse bias stress (HTRB at 150℃ 1000h) and wafer baking (at 250℃ 120h) tests. The behavior of DC parameters such as threshold voltage, maximum of transconductance in linear region, on-resistance in linear region, drain leakage current, gate leakage current and drain-source breakdown voltage, is deduced from HP4145B Semiconductor Parameter Analyzer measurements and analyzed. During the baking, this study focuses on N+ contact resistance and on-resistance stabilities. All these analyses demonstrate the high reliability of these power devices.