Polysilicon oxide quality optimization at wafer level of a Bipolar/CMOS/DMOS technology

摘要

Inter-polycrystalline silicon oxide capacitor, further called, “polysilicon oxide”, is one of the peculiarities of Bipolar/CMOS/DMOS process. The oxidation of polycrystalline silicon generates poor polysilicon/oxide interface quality, in comparison with mono-crystalline silicon one, because different ratios of oxidation exist between grains and grains boundaries. This implies a decreasing of the oxide strength from 10 MV/cm (oxide on mono-crystalline silicon and same thickness) to 7 MV/cm. The optimization of this oxide needs specific approaches of process and of reliability test. After presentation of polysilicon oxide process, this paper deals with optimization of the quality of this oxide using several approaches and tested at wafer level with specific test masks. To shorten the quality evaluation measurement of this oxide, a correlation between voltage and breakdown electrical field is established and discussed; this correlation allows establishing a rapid wafer level estimation at parametric test level and acts as a quality indicator. This wafer level techniques is applied on Bipolar/CMOS/DMOS technology.