A simplified yield modeling method for design rule trade-off in interconnection substrates

摘要

In this paper, we present a pre-layout yield estimation approach to assess the impact of changing design rules to overall substrate cost. Introducing a density factor for interconnect substrates together with a simplified yield model, thus accelerating the “short failure” critical area estimation, a preliminary design rule trade-off is feasible. In order to assess a possible cost impact when changing the design rules, we used a nine-chip Pentium multi-chip module as a case study, where we re-calculated substrate sizes and first pass yields using our model. The results showed that there is only a narrow window of opportunity to profit economically from altering the rules.