A study of advanced layout verification to prevent leakage current failure during power down mode operation

摘要

Today, portable devices such as PDA and mobile phone etc. are becoming more and more common with the advance in the integration technology of semiconductor chips. One of the important issues with those portable devices is power consumption caused by the leakage and the operating current of a chip, because battery power is used for operation. There are varieties of techniques used at the design level as well as at the device and process level to reduce such currents. However, there can be source of unwanted leakage current mainly due to the complex vertical structure of devices.