Novel FIB-based sample preparation technique for TEM analysis of ultra-thin gate oxide breakdown

摘要

For gate oxides of less than5 m thickness, the damage area of a breakdown site is expected to be very small, and probably close to the atomic scale as discussed for soft breakdown events. It is very difficult to prepare a TEM-lamella that contains a nanometer-sized feature. In a new approach, a lamella is prepared containing the complete transistor with the breakdown site. This technique is introduced, and first promising results are discussed. It will be especially useful for short-channel transistors in emerging CMOS technologies.