Defects in silicon oxynitride gate dielectric films

摘要

As the aggressive scalling of the metal-oxide-semiconductor structure continues, new reliability challenges in gate dielectric materials now came across as the gate dielectric thickness will be further down scaled to its technological constraint (<3 nm). Since the interface thickness and the capture cross-section of dielectric trps are not scalable, the nano device structures and the giga-scale circuit architectures call for a fabrication process with ultra-high uniformity and repeatability for devices. These put strengthen constraints on the trap density and chemical composition fluctu- ations of the gate dielectric materials.