Atomic-layer-deposited silicon-nitride/SiO_2 stack ― a highly potential gate dielectrics for advanced CMOS technology

摘要

An extremely thin (～ 2 monolayers) silicon nitride layer has been deposited on thermally grown SiO_2 by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal-oxide-semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_(eq) = 2.2 nm) efficiently reduce the boron diffusion from p~+ poly-Si gate without the pile up of nitrogen atoms at the SiO_2/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO_2 especially in the thin (<0.5 nm) thickness region. An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO_2 stack gate dielectrics compared with those of conventional SiO_2 dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO_2 and SiO_2/Si-substrate interfaces for the SiO_2 gate dielectrics and only near the SiO_2/ Si-substrate interface for the stack gate dielectrics. Employing annealing in NH_3 at a moderate temperature of 550℃ after the ALD of silicon nitride on SiO_2, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH_3 annealing. Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.