Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

摘要

this paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in lyout area efficiency, bus resistance tolerance, design modularity, and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results.