Robustness improvement of VDMOS transistors in Bipolar/CMOS/DMOS technology

摘要

This paper presents results of reliability investigation of power VDMOSFET in a Bipolar/CMOS/DMOS technology. In most cases the mechanisms that degrade these devices are due to mobile and interface charges, incorporated during process steps. Process robustness with efficiency of phosphorus content as gettering agent, in BPSG layer, is performed on VDMOS transistor after controlled sodium incorporation. The reliability tests are performed with classical HTRB on encapsulated components (HTRB at 150℃ - 1000h) and accelerated HTRB at wafer level (at 300℃ during 1h).