A study of considering the reliability issues on ASIC/Memory integration by SIP (System-in-Package) technology

摘要

This paper presents some considerations about reliability issues when we intend to make more than one chip in one package, so-called SIP (System-in-Package) technology, in order to mainly take advantage of the size reduction. Usually the rate of size reduction is approximately 30～60% on the identical printed circuit board. So SIP technology can be used for portable devices such as mobile phone, PDA (Personal Digital Assistants), camcorder and others. Recently increasing more functionality of those devices leads to use more memories. On the other hand, the size of printed circuit board should be same as before or even smaller than before. Therefore SIP technology will be good solution for that matter. In this paper, we look into the advantages of using SIP first, and then look around about the reliability issues such as leakage current, Test, EMI (Electromagnetic Interference), EOS (Electrical Over Stress) and latch-up related to using SIP. Some design guides to bypass those issues are proposed in this paper.