Improvement of integrated circuit testing reliability by using the defect based approach

摘要

The systematic decrease in the minimum feature size in VLSI circuits makes spot defects an increasingly significant cause of ICs' faults. A testing method optimized for detecting faults of this origin has been recently developed. This method, called defect based testing (DBT), requires a lot of computational effort at the stage of testing-procedure preparation, which makes it appear less attractive than the well-known stuck-at-fault oriented testing. This paper, however, shows that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults. Experiments with the C17 ISCAS-85 testability benchmark show that the risk of a spot-defect damaged circuit passing the test is dangerously high if the test set was designed with stuck-at-faults in mind. It is also shown that although spot defects may in some cases transform a combinational circuit into a sequential one, in practice this phenomenon does not require any special treatment from the test designer. Eventually, a few methods are discussed that make the DBT less time consuming.