MSOH processor for STM-0/STS-1 to STM-4/STS-12: component of a SDH/SONET library

摘要

The purpose of this paper is to show the requirement specification, the architecture and verification of the designed component for the multiplex section overhead processing for transmission systems using a SDH/SONET data stream for STM-0/STS-1 to STM-4/STS-12 signals (ITU-T, Telecommunication Standardization Sector of ITU. G.707; ITU-T, Telecommunication Standardization Sector of ITU. G.783). Its purpose is to allow the fast design of network elements. This component calculates the bit error in each of the STM-0/STS-1, bit error per frame, block error per frame, bit and block error in one second, signal failure and signal degrade conditions, bytes filtering and far end error reporting. Some advantages respect other components in the market are obtained. This component for a SDH/SONET library has been coded using VHDL, verified and synthesized using Synopsys tools.