Study and validation of a power-rail ESD clamp in BiCMOS process with a reduced temperature dependency of its leakage current

摘要

In this paper, we present a study, development and qualification of an improved power-rail ESD clamp (called "RC-PSC") in a 40 GHz BiCMOS process. The leakage of the previous version of the clamp (called "6d-PSC") showed a strong dependence on temperature, resulting in failures during HTOL (High Temperature Operational Life) and latchup testing. At 150℃ and supplied at 3.3V, the leakage current has been successfully reduced from 40 μA to 30 nA, without a degradation of ESD robustness.