Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress

摘要

Smart power SOI technology electrostatic discharge (ESD) protection devices are investigated under the transmission line pulser (TLP) and very-fast TLP stress. Thermal and free carrier distributions in the Si active layer during the stress are measured by transient interferometric mapping (TIM) method. It is shown that in contrast to measurements in bulk structures, the TIM phase signal in SOI structures is affected by multiple reflections within the Si active layer. The influence of the thickness of the Si active and oxide layers on the phase signal is investigated by optical matrix simulation. The triggering homogeneity, hot spots and carrier injection places are analysed in devices with a circular and linear geometry and correlated with results of device simulation.