A Novel Automatic Polishing Technique for Micro-Controllers with 45° off Si < 100 > Rotation

摘要

With scaling down of Integrated Circuits (IC) critical dimensions, the proportion of leakage current has increased drastically. ATMEL utilizes a novel technology based on 45° rotation relative to Si < 100 > (c-flat) for reducing channel leakage current in CMOS devices. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current was reduced by up to two orders of magnitude for a 0.21 μm N-channel CMOS device. The 45° rotation technology poses several challenges for traditional Failure Analysis (FA) methods like cleaving and polishing. The metal/polysilicon features no longer align with the cleave plane, requiring special cleaving at 45°. The sharp edge and the differential increase in the polished area cause difficulties in controlling the process manually. An innovative technique, developed by Sagitta, for cleaving and automatic polishing of rotated Si devices for FA and process control monitoring will be discussed in this paper.