Electrostatic Effects on Semiconductor Tools

摘要

The paper describes physical details of process-tool-induced surface ESDFOS (Electrostatic Discharge From Outside-to-Surface). In many post-wafer processes, electrostatic discharge takes place by charged handlers, chip pickers etc. Or, on the other hand, singular devices suffered charging on blue foil, carrier tapes, etc. In all these cases, the discharge impact breaks through the passivation and destructs the device surface; in most cases, short-circuits between the two top metal layers result. The mechanism and its latency risk is described well in a recent publication of JMR. This paper now shows the different grades of discharge severeness, how to recognise best the failure mechanism and some estimations considering voltage and energy. Practical experience has shown that, over the whole branch, in many cases, a misinterpretation takes place, when visual inspections found such kind of failures: Most of them have been put into the category "Mechanical Damage" and thus, the root cause remains undiscovered.