Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5-2 nm thick gate-oxides

摘要

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_(ox) = 2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above -1.8 V. Devices with T_(ox) = 6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging-discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.