Electrical Performance Evaluation of FIB Edited Circuits through Chip Backside Exposing Shallow Trench Isolations

摘要

Circuit edit, critical to design validation, is challenged by shrinking dimensions for which an accurate alignment is mandatory. Possible alignment features are in lower metal levels, Poly-silicon and STI structures. STI structures are the first encountered in case of editing through the chip backside and accurate CAD alignment requires trenching until the lower STI edge becomes visible. The impact to device performance in exposing these is examined. Only minor performance changes occur.