Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models

摘要

Two models for the effect of area scaling on reliability are derived from two distinct yield models with different assumptions on defect distributions. One is derived from the Poisson yield model assuming a uniform random distribution of defects as in an early model. The other is based on the negative binomial yield model to account for deviation from a uniform random distribution of defects caused by clustering. Experimental data from backend test structures show that the model based on defect clustering explains observed data well while the model assuming a uniform random distribution shows a significant departure from it.