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首页> 外文期刊>Microelectronics & Reliability >Pre- and post-BD electrical conduction of stressed HfO_2/SiO_2 MOS gate stacks observed at the nanoscale
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Pre- and post-BD electrical conduction of stressed HfO_2/SiO_2 MOS gate stacks observed at the nanoscale

机译:在纳米级观察到的应力HfO_2 / SiO_2 MOS栅叠层的BD前后导电

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摘要

In this work, the electrical properties of fresh and stressed HfO_2/SiO_2 gate stacks have been studied using a prototype of Conductive Atomic Force Microscope with enhanced electrical performance (ECAFM). The nanometer resolution of the technique and the extended current dynamic range of the ECAFM has allowed to separately investigate the effect of the electrical stress on the SiO_2 and the HfO_2 layer of the high-k gate stack. In particular, we have investigated this effect on both layers when the structures where subjected to low and high field stresses.
机译:在这项工作中,已经使用具有增强电性能(ECAFM)的导电原子力显微镜原型研究了新鲜的HfO_2 / SiO2应力栅堆叠和SiO2栅堆叠的电气性能。该技术的纳米分辨率和ECAFM的扩展电流动态范围已使我们能够分别研究电应力对高k栅极堆叠的SiO_2和HfO_2层的影响。尤其是,我们已经研究了当结构受到低场应力和高场应力时对两层的影响。

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