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Reliability challenges for copper low-k dielectrics and copper diffusion barriers

机译:铜低k电介质和铜扩散势垒的可靠性挑战

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摘要

The performance of interconnects containing micro- (pore size smaller than 2 nm) and meso-porous (pore size larger than 2 nm) interlevel dielectrics is influenced by material selection, integration scheme and virtually all fabrication steps. It is generally reported that the reliability margin of the dielectric/barrier/copper system is shrinking. Barrier and dielectric integrity play a most important role in line-to-line leakage and Time Dependent Dielectric Breakdown (TDDB) reliability. TDDB has never been an issue for Cu-SiO_2 interconnects, but for sub-100 nm copper/barrier/low-k systems it becomes challenging. When monitoring the integrated dielectric properties early failures can be caused by weak integration interfaces, dielectric damage during the integration, defective diffusion barrier or other non-uniformities related to the damascene process. Recent advances are reviewed along with examples and reference to state of the art.
机译:包含微米级(孔径小于2 nm)和中孔级(孔径大于2 nm)层间电介质的互连性能受材料选择,集成方案以及几乎所有制造步骤的影响。通常据报道,电介质/阻挡层/铜系统的可靠性裕度正在缩小。阻挡层和介电完整性在线间泄漏和随时间变化的介电击穿(TDDB)可靠性中起着最重要的作用。对于Cu-SiO_2互连,TDDB从来都不是问题,但是对于低于100 nm的铜/势垒/低k系统而言,它变得充满挑战。监视集成介电性能时,早期故障可能是由于集成界面薄弱,集成过程中的电介质损坏,有缺陷的扩散势垒或其他与镶嵌工艺有关的不均匀性所致。回顾了最新的进展以及示例,并参考了最新技术。

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