Efficient parametric yield optimization of VLSI circuit by uniform design sampling method

摘要

A novel yield estimation and optimization method is proposed based on uniform design sampling (UDS) method, which is one kind of quasi-Monte Carlo method. Compared with primitive statistical methods based on Monte Carlo sampling method, this new method needs only few circuit simulations to have a valuable estimation and is immune to the number of statistical variables. Furthermore, owing to simple algorithm to generate samples, the UDS method adds no computational complexity. A comparison of UDS method with the popular Monte Carlo based method-Latin hypercube sampling method is made in this paper to show the efficiency of the new method. Finally, several examples are presented to demonstrate the advantages of the proposed method over those available.