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Backside interferometric methods for localization of ESD-induced leakage current and metal shorts

机译:用于确定ESD引起的漏电流和金属短路的背面干涉法

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摘要

Transient interferometric mapping (TIM) setup for ns-time ESD testing is adapted for post-stress failure analysis. Probing from the chip backside using the thermo-optical effect is used for localization of heating place related to failure. Two variants of 2D holographic interferometers, a Michelson and a "Wollaston" one, are used for a rough identification of a failure site. An adapted scanning heterodyne interferometer is used for accurate position determination with a 2 μm space resolution. The methods are applied to identify ESD damage and metal shorts. Sensitivity and space resolution are analyzed, supported by a 3D-thermal simulation of repetitive heating signal. A power sensitivity of 50 μW for a single point heat source is demonstrated.
机译:用于ns时间ESD测试的瞬态干涉图(TIM)设置适用于应力后故障分析。利用热光效应从芯片背面进行探测可用于定位与故障相关的加热位置。二维全息干涉仪的两种变体,一种是迈克尔逊型,另一种是“ Wollaston”型,用于粗略地确定故障部位。适配的扫描外差干涉仪用于2μm空间分辨率的精确位置确定。该方法适用于识别ESD损坏和金属短路。在重复加热信号的3D热模拟的支持下,分析了灵敏度和空间分辨率。单点热源的功率灵敏度为50μW。

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