A comprehensive study of stress induced leakage current using a floating gate structure for direct applications in EEPROM memories

摘要

The aim of this study is to obtain from experimental data a reliable approach for predicting the impact of temperature on data retention in EEPROM memories. Using a floating gate dedicated structure, we present stress induced leakage current results and characterization in terms of AC generation, annealing kinetics and temperature activation in 6.8 nm SiO_2 tunneling oxide used in standard EEPROM products. We propose a simple way to deal with these three aspects in order to describe SILC evolution during retention phases corresponding to an oxide floating gate potential lower than 2 V.