Advanced backside failure analysis in 65 nm CMOS technology

摘要

Due to reducing size of elementary devices, increasing number of metallization levels and decreasing of power supply voltage, the debug and failure analysis of advanced CMOS designs requires the implementation of specific backside sample preparation methodologies and backside measurement flow. This paper describes the diagnosis and backside failure analysis flow implemented to successfully debug a flip-flop cell designed in 65 nm CMOS technology.