ESD protection strategies in advanced CMOS SOI ICs

摘要

This paper represents a part of the ESREF 2007 tutorial on the design of IC protection circuits built with advanced deep sub-microi CMOS silicon-on-insulator (SOI) technologies. The tutorial covers fundamental aspects of active rail clamp Electrostatic Discharg (ESD) protection approach to meet the human body model (HBM), machine model (MM), and charged device model (CDM) require ments in SOI ICs. The paper focuses on 65 nm SOI ESD protection network and design methodology including both device and circui level characterization data. It compares pulsed measurement results of SOI MOSFETs and diodes to bulk devices. It also introduces i response surface method (RSM) to optimize device sizes in the ESD networks.