On chip-package stress interaction

摘要

In this paper, the interaction between chip and package is investigated. A series of experiments are conducted to investigate the effect of the package type on occurrence of passivation cracks in IC structures. Virtual prototyping is used to generate more accurate and efficient stress design rules for IC backend structures, in combination with packaging processes and geometry. The addressed failure mode of passivation cracks is found to depend on the package type or family: for exposed pad packages this failure mode is easier to occur. It is demonstrated that for successful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC back-end development. The so-called integral design rules, accounting for all the major loading sources and history of the complete product creation process has to be used for the development of new generation semiconductors devices.