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Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs-InGaAs symmetric double-gate HEMT

机译:连接和分离的纳米级InAlAs-InGaAs对称双栅极HEMT的异质界面电势和阈值电压建模

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摘要

This paper presents an approximate solution of a 2-D Poisson's equation in the channel region, based on physical correspondence between MOSFET and HEMT, with the approximation that the vertical channel potential distribution is a cubic function of position to study not only tied gate but separate gate bias conditions as well. An analytical expression for both front and back heterointerface potential is derived and threshold voltage is obtained iteratively from the proposed potential model. The threshold voltage behavior for tied and separated double-gate HEMT is investigated for various device dimensions. The back gate effect of the separated double gate HEMT is investigated for the depleted back channel only. The results obtained are verified by comparing them with simulated and experimental results.
机译:本文基于MOSFET与HEMT之间的物理对应关系,给出了沟道区中二维Poisson方程的近似解,并近似得出垂直沟道电势分布是位置的三次函数,不仅研究了束缚栅而且还研究了分离栅栅极偏置条件也是如此。推导了正面和背面异质界面电势的解析表达式,并从提出的电势模型中迭代获得了阈值电压。对于各种器件尺寸,研究了束缚和分离双栅极HEMT的阈值电压行为。仅针对耗尽的反向沟道研究了分离的双栅极HEMT的反向栅极效应。通过将它们与模拟和实验结果进行比较来验证所获得的结果。

著录项

  • 来源
    《Microelectronics reliability》 |2009年第12期|1508-1514|共7页
  • 作者单位

    Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110 021, India;

    Department of Physics and Electronics, A.R.S.D. College, University of Delhi South Campus, New Delhi, India;

    Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110 021, India;

    Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110 021, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
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