Experimental and simulated dc degradation of GaN HEMTs by means of gate-drain and gate-source reverse bias stress

摘要

In this paper, the degradation of AlGaN/GaN high-electron mobility transistors (HEMTs) is investigated by means of dc stresses performed on fresh devices either on the gate-drain junction only (i.e., with the source terminal floating) or on the gate-source junction only (i.e., with the drain terminal floating). In both cases step-stresses were carried out by increasing V_(dg) and V_(SG) respectively up to 35 V: the saturated drain current decreased in both cases, and a significant increase in the output conductance was found for the drain-stressed devices, whereas it was negligible for the source-stressed devices. The reason for these different behaviors was believed to be the creation of acceptor traps in the AIGaN layer underneath the stressed side of the gate junction, their influence being different in the two cases because of the high horizontal electric field at the drain end of the gate during on-state operation. We carried out numerical simulations showing that the presence of a defective region with an acceptor trap concentration underneath the gate-drain or gate-source junction fits our hypothesis.