Ultra-fast CAD scan chain highlighting for failure analysis assistance

摘要

Automatic test pattern generation (ATPG) and scan tests are common design for testability methods (DfT) for digital logic ICs. A prerequisite for structural logic tests is the integrity of the embedded test circuit itself, i.e. the scan flipflops that are stringed together in scan chains. If there is a failure within one of the scan chains, localization can be quite challenging. One particular problem for failure analysis engineers is the CAD navigation along the chain: in order to display the physical position of a scan chain, hundreds or even thousands of flipflops have to be cross-mapped between the design netlist and the physical layout. This task requires extensive computing and can be very time-consuming. The work described in this paper is a new data processing method that reduces the required computing time from several hours down to a few seconds.