Quantum circuit's reliability assessment with VHDL-based simulated fault injection

摘要

This paper presents a VHDL-based simulated fault injection (SF1) methodology for quantum circuits. The main objective is to attain a high error modeling capability at a technology independent level. For this purpose, gate level simulation models for quantum circuits have been developed using VHDL The proposed methodology relies on specific techniques inspired from the simulated fault injection techniques developed for classical CMOS circuits: saboteurs and mutants. In order to perform the simulation campaigns, a library of quantum gates and simulated fault injection components has been developed. The simulation results show that a wide range of quantum faults and error models has been addressed. Furthermore, a comparison between the two SFI techniques is presented.