LDMOSFET with drain potential suppression for 100 V Power IC technology

摘要

A standard 0.35 micrometer CMOS technology has been extended for 100 V Power IC applications by accommodating reduced surface field (RESURF) LDMOSFET device with p-well block region or extended poly-overlap region for suppression of the drain wrapping potential. A 100 V integrated H-bridge circuit suitable for driving a brushless DC motor has been designed, manufactured and tested to prove the technology. To streamline the design and integration of this power device 2D and 3D simulations have been performed. Different electrical isolation schemes to provide technology compartmentalization have also been investigated experimentally and results are discussed.