Electromigration failure in a copper dual-damascene structure with a through silicon via

摘要

Electromigration induced failure development in a copper dual-damascene structure with a through silicon via (TSV) located at the cathode end of the line is studied. The resistance change caused by void growth under the TSV and the interconnect lifetime estimation are modeled based on analytical expressions and also investigated with the help of numerical simulations of fully three-dimensional structures. It is shown that, in addition to the high resistance increase caused by a large void, a small void under the TSV can also lead to a significant resistance increase, particularly in the presence of imperfections at the TSV bottom introduced during the fabrication process. As a consequence, electromigration failure in such structures is likely to have bimodal characteristics. The simulation results have indicated that both modes are important to be considered in order to obtain a more precise description of the interconnect lifetime distribution.