Design issues of a thin-film p-channel SOI power MOSFET for high-temperature applications

摘要

In recent years, high-temperature applications of power ICs have attracted significant attention, and thin-film SOI approach is one of the promising candidates. p-Channel power MOSFETs are essential components of power ICs. This paper reports on the high-temperature device characteristics of the thin-film SOI reduced surface field (RESURF) p-channel SOI power MOSFETs and the design issues for high-temperature applications (＞573 K) on the basis of the experimental results and 2-D device simulations. The results show that the thinner top silicon layer is preferable for high-temperature applications to suppress the increasing on-resistance, and a thinner gate oxide is preferable to suppress the decrease in the threshold voltage and increase in the subthreshold slope with increasing temperature.