Delay fault testing using partial multiple scan chains

摘要

Delay test patterns can be generated at the functional level of the circuit using a software prototype model, when the primary inputs, the primary outputs and the state variables are available only. Functional delay test can be constructed for scan and non-scan sequential circuits. Functional delay test constructed using software prototype model can detect transition faults at the structural level quite well. Therefore, we propose a new iterative functional test generation approach. The proposed approach involves a partial multiple scan chain construction using the results of functional delay test generation at a high level of abstraction. The iterativeness of the method allows finding the compromise between the test coverage, hardware overhead and test length. Furthermore, using the partial multiple scan chains requires less hardware overhead resulting in shorter test application times. The experimental results are provided for the ITC'99 benchmark circuits. Experiments showed that the obtained transition fault coverage is on average 2% higher than using full scan and commercial automatic test pattern generator for transition faults.