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Modelling methodology for thermal analysis of hot solder dip process

机译:热浸焊工艺热分析的建模方法

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摘要

The shift of electronics industry towards the use of lead-free solders in components manufacturing brought also the challenge of addressing the problem of tin whiskers. Manufacturers of high reliability and safety critical equipment in sectors such as defence and aerospace rely increasingly on the use of commercial-of-the-shelf (COTS) electronic components for their products and systems. The use of COTS components with lead-free solder plated terminations comes with the risks for their long term reliability associated with tin whisker growth related failures. In the case of leaded type electronic components such as Quad Flat Package (QFP) and Small Outline Package (SOP), one of the promising solutions to this problem is to "re-finish" the package terminations by replacing the lead-free solder coatings on the leads with conventional tin-lead solder. This involves subjecting the electronic components to a post-manufacturing process known as Hot Solder Dip (HSD). One of the main concerns for adopting HSD (refinishing) as a strategy to the tin whisker problem is the potential risk for thermally induced damage in the components when subjected to this process. This paper details a thermal modelling driven approach to the characterisation of the impact of hot solder dipping on electronic components. Main focus is on the evaluation of the re-finishing process effects on parts' temperature gradients and heating/cooling rates, and on the advantages of applying an efficient model based process optimisation. Transient thermal finite element analysis is used to evaluate the temperature distribution in Quad Flat Package (QFP) variants during a double-dip hot solder dipping process developed by Micross Components Ltd. Full detailed three-dimensional (3D) models of the components are developed using comprehensive characterisation of the respective package structures and materials based on X-ray, SEM-EDX, cross-sectional metallurgy and 3D CT scan. The thermal modelling approach is validated using thermocouple measurement data for one of the studied parts and by comparing with model temperature predictions. Model results have informed the process optimisation strategy, and through experimentation key process parameters are alerted to provide optimal thermal characteristics. The optimised process settings result in temperature ramp rates at die level within recommended manufacture's limit. A demonstration and discussion on the influence of the package internal structure and design on the thermal response to HSD is also provided.
机译:电子行业向组件制造中使用无铅焊料的转变也带来了解决锡晶须问题的挑战。国防和航空航天等领域中具有高可靠性和安全性至关重要的设备的制造商越来越依赖于在其产品和系统中使用现成的(COTS)电子组件。将COTS组件与无铅镀锡端子配合使用会带来与锡晶须生长相关的故障相关的长期可靠性风险。对于四方扁平封装(QFP)和小尺寸封装(SOP)等引线式电子组件,解决此问题的一种有希望的解决方案是通过替换无铅焊料涂层来“重新整理”封装端子用传统的锡铅焊料在引线上。这涉及对电子组件进行后制造过程,即热焊浸(HSD)。采用HSD(修补)作为锡晶须问题的策略的主要问题之一是,经过此工艺后,组件中可能会因热引起损坏。本文详细介绍了一种热模型驱动的方法来表征热浸焊料对电子元件的影响。主要重点是评估再加工过程对零件的温度梯度和加热/冷却速率的影响,以及应用基于模型的有效过程优化的优势。瞬态热有限元分析用于评估Micross Components Ltd开发的双浸热焊料浸渍过程中四方扁平封装(QFP)的温度分布。使用以下方法开发了组件的完整详细三维(3D)模型基于X射线,SEM-EDX,截面冶金学和3D CT扫描,对各个封装结构和材料进行全面表征。使用所研究零件之一的热电偶测量数据并与模型温度预测值进行比较,可以验证热建模方法。模型结果告知了工艺优化策略,并通过实验提醒了关键工艺参数,以提供最佳的热特性。优化的工艺设置可以使芯片级的温度上升速率在建议的制造极限之内。还提供了封装内部结构和设计对HSD热响应影响的演示和讨论。

著录项

  • 来源
    《Microelectronics & Reliability 》 |2013年第8期| 1055-1067| 共13页
  • 作者单位

    Computational Mechanics and Reliability Group, University of Greenwich, London SE10 9LS, UK;

    Computational Mechanics and Reliability Group, University of Greenwich, London SE10 9LS, UK;

    Computational Mechanics and Reliability Group, University of Greenwich, London SE10 9LS, UK;

    Computational Mechanics and Reliability Group, University of Greenwich, London SE10 9LS, UK;

    School of Engineering, University of Greenwich, Chatham Kent ME4 4TB, UK;

    Micross Components Ltd., 11-16A-Tech Court, Lancasterfields Crewe CW1 6FF, UK;

    Micross Components Ltd., 11-16A-Tech Court, Lancasterfields Crewe CW1 6FF, UK;

    Micross Components Ltd., 11-16A-Tech Court, Lancasterfields Crewe CW1 6FF, UK;

    SELEX Galileo Ltd., Crewe Toll, Ferry Road, Edinburgh EH5 2XS, UK;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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