The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET

摘要

The impact of interface/border defect on performance and reliability was investigated for gate-first and gate-last high-k/metal-gate CMOSFET. For high-k/metal-gate CMOSFET, V_(FB) roll-off is critical as effective oxide thickness (EOT) scales below 15 angstrom (A) especially for metal gate-first device with an extra capping layer to adjust V_(TH). By proposing a model of metal-gate process induced interface trap releasing oxygen, the vertical and lateral interface trap distribution and the dependence of interfacial layer (IL) on V_(FB) roll-off phenomena can be well interpreted. In this work, we found that V_(FB) roll-off can be improved by reducing oxygen vacancy (V_O) at the HfO_2/IL interface with suppression of oxygen diffusion from high-k to IL By the way, a metal gate-last process with lower interface trap was proposed to minimize V_O formation by suppress oxygen releasing, thus optimize a 28 nm 15 A EOT HfO_2/metal-gate CMOSFET with low V_(FB)-EOT roll-off, it can be a reference for sub 22 nm CMOSFET with thin EOT (<15 A) design.