vfTLP-V_(TH): A new method for quantifying the effectiveness of ESD protection for the CDM classification test

摘要

A new methodology tor quantifying the effectiveness of CDM protection circuits and CDM robustness of I/ 0 circuits is presented in this paper. This method, referred to as the vfTLP-V_(TH), consists of applying vfTLP stresses to test structures composed of the ESD protection and the device or circuit to be protected: a MOS device or a MOS inverter. The protected structures are used as monitors and shifts in their characteristics, such as MOS threshold voltage V_(TH) and saturation current I_(DD), are used to probe device failure criteria.