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Reliability of micro-interconnects in 3D IC packages

机译:3D IC封装中微互连的可靠性

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摘要

As shrinking of the critical dimensions in integrated circuits becomes increasingly difficult, semiconductor industry resorts to other approaches to achieve the objective of building new devices that consume less power but have higher performance. To this end, the three dimensional integrated circuits (3D ICs) architecture is favored by many semiconductor companies. The stacking of chips in 3D ICs architecture allows for higher performance in much smaller packages. While substantial resources have been invested on resolving the design and processing issues, 3D integration still faces serious materials and reliability challenges.
机译:随着集成电路中关键尺寸的缩小变得越来越困难,半导体行业采用其他方法来实现构建功耗更低但性能更高的新器件的目标。为此,许多半导体公司都偏爱三维集成电路(3D IC)体系结构。 3D IC体系结构中的芯片堆叠可在小得多的封装中实现更高的性能。尽管已投入大量资源来解决设计和处理问题,但3D集成仍面临严重的材料和可靠性挑战。

著录项

  • 来源
    《Microelectronics & Reliability》 |2013年第1期|1-1|共1页
  • 作者单位

    Department of Materials Science and Engineering,National Taiwan University, Taipei 10617, Taiwan;

    Department of Chemical and Materials Engineering,National Central University, Jhongli 32001, Taiwan;

    Department of Materials Science and Engineering,University of California at Los Angeles, Los Angeles,CA 90095-1595, USA;

    Advanced Semiconductor Engineering, Inc., Kaohsiung 81170, Taiwan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
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