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Analysis of flicker and thermal noise in p-channel Underlap DG FinFET

机译:p通道Underlap DG FinFET中的闪烁和热噪声分析

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摘要

In this paper, we analyze the flicker and thermal noise model for underlap p-channel DG FinFET in weak inversion region. During the analysis of current and charge model, minimum channel potential i.e. virtual source is considered. Initially, the drain current for both long and short channel of DG FinFET are evaluated and found to be well interpreted with experimental results. Further, the flicker and thermal noise spectral density are derived. The flicker noise power spectral density is compared with published experimental results, which shows a good agreement between proposed model and experimental result. During calculation we have considered variation of scattering parameter and furthermore, the degradation of effective mobility is taken into account for ultrathin body. The variation of structural parameters such as gate length (L_g), body thickness (t_(Si)) and underlap length (L_(un)) are also considered. The degradation of gate noise voltage with frequency, underlap length and gate length signify that p-channel DG FinFET device can be a promising candidate for analog and RF applications.
机译:在本文中,我们分析了弱反转区域中的重叠p沟道DG FinFET的闪烁和热噪声模型。在分析电流和电荷模型期间,要考虑最小的通道电势,即虚拟源。最初,对DG FinFET的长沟道和短沟道的漏极电流进行了评估,并发现可以用实验结果很好地解释。此外,导出了闪烁和热噪声频谱密度。将闪烁噪声功率谱密度与已发表的实验结果进行了比较,表明所提出的模型与实验结果之间具有很好的一致性。在计算过程中,我们考虑了散射参数的变化,此外,对于超薄体,还考虑了有效迁移率的降低。还考虑了诸如门长度(L_g),车身厚度(t_(Si))和搭接长度(L_(un))之类的结构参数的变化。栅极噪声电压随频率,重叠长度和栅极长度的降低表明,p沟道DG FinFET器件可以成为模拟和RF应用的有前途的候选者。

著录项

  • 来源
    《Microelectronics & Reliability》 |2014年第8期|1549-1554|共6页
  • 作者单位

    Nano Device Simulation Laboratory, Electronics and Telecommunication Engineering Department, Jadavpur University, Kolkata 700 032, India;

    Nano Device Simulation Laboratory, Electronics and Telecommunication Engineering Department, Jadavpur University, Kolkata 700 032, India;

    Silicon Institute of Technology, Patia Hills, Bhubaneswar 751024, India;

    Nano Device Simulation Laboratory, Electronics and Telecommunication Engineering Department, Jadavpur University, Kolkata 700 032, India;

    Nano Device Simulation Laboratory, Electronics and Telecommunication Engineering Department, Jadavpur University, Kolkata 700 032, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Ultrathin body; p-Channel; Underlap DG FinFET; Virtual source; Flicker noise; Thermal noise;

    机译:超薄机身p通道;Underlap DG FinFET;虚拟源;闪烁噪声;热噪声;

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