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An 8-level 3-bit cell programming technique in NOR-type nano-scaled SONOS memory devices

机译:NOR型纳米级SONOS存储设备中的8级3位单元编程技术

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摘要

An 8-level 3-bit cell programming technique is presented in NOR-type nano-scaled polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) memory devices. This new operating mode provides the double programming and sensing window over the traditional 4-level cell programming by using a double-side hot hole injection erasing. Compared with the 4-level cell, the storage density of the 8-level cell is greatly improved. However, the cycling endurance and retention properties are not obviously degraded until 1000 program/erase cycling.
机译:在NOR型纳米级多晶硅氧化硅,氮化物,氧化硅(SONOS)存储设备中提出了一种8级3位单元编程技术。这种新的工作模式通过使用双面热空穴注入擦除功能,在传统的4级单元编程上提供了双重编程和感应窗口。与4级单元相比,8级单元的存储密度大大提高。但是,直到1000次编程/擦除循环后,循环耐久性和保留性才明显降低。

著录项

  • 来源
    《Microelectronics & Reliability》 |2014年第1期|331-334|共4页
  • 作者单位

    College of Electronic Science & Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China,College of Electronic Science & Engineering, Nanjing University, Nanjing 210093, China;

    College of Electronic Science & Engineering, Nanjing University, Nanjing 210093, China;

    College of Electronic Science & Engineering, Nanjing University, Nanjing 210093, China;

    College of Electronic Science & Engineering, Nanjing University, Nanjing 210093, China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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