PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

摘要

Increasing in device parameter variations is the critical issue in very deep sub-micron regime due to continue scaling of the transistor dimensions. The overall performance yield of the logic circuit is diminished by raising leakage current and variability issues in scaled devices. In this article; we have proposed an approach called INDEP, based on Boolean logic calculation for the input signals of the extra inserted transistors between the pull-up and pull-down network of the CMOS logic. INDEP approach is not only reduces the leakage current but also mitigates the variability issues with minimum susceptible delay paths. Various process, voltage and temperature (PVT) variations are analyzed at 22 nm BS1M4 bulk CMOS PTM technology node for chain of 5-inverters using HSPICE tool. Several guidelines are provided to design the variability aware CMOS circuits in nanoscale regime by considering the leakage current variation. INDEP approach works effectively in both active as well as standby state of the circuit and keeping the modal performance characteristics of the CMOS gate. The electrical simulation results show that our proposed INDEP approach is less susceptible to PVT variations as compared to conventional circuit. The Monte-Carlo simulation results confirm that average INDEP leakage current reduction is 62.31% at ±20% PVT variations under 3a Gaussian distribution for chain of 5-inverters.