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Reliability studies of vertical GaN devices based on bulk GaN substrates

机译:基于块状GaN衬底的垂直GaN器件的可靠性研究

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There is great interest in wide band-gap semiconductor devices and most recently in vertical GaN structures for power electronic applications. In this paper initial reliability studies of vertical p-n diodes and vertical junction field effect transistors fabricated on pseudo bulk low defect density (10(4) to 10(6) cm(-2)) GaN substrates are discussed. Homoepitaxial MOCVD growth of GaN on its native substrate and being able to control the doping in the drift layers in GaN has allowed the realization of vertical device architectures with drift layer thicknesses of 6 to 40 pm and net carrier electron concentrations of 2 x 10(15) to 2 x 10(16) cm(-3). This parameter range is suitable for applications requiring breakdown voltages of 1200 V to 5 kV with a proper edge termination strategy. Measured devices demonstrate power device figure of merit of differential specific on-resistance (R-sp) of 2.8 m Omega-cm(2) for a breakdown voltage of 4.1 kV. The improvement in the substrate quality over the last few years has resulted in the fabrication of diodes with areas as large as 16 mm(2), with breakdown voltages exceeding 1200 V, and pulsed (100 mu s) currents of 100-400 A. Furthermore, impact ionization based avalanche breakdown has been demonstrated in GaN for the first time due to the high quality of the crystals grown on the native substrates. With these key demonstrations firmly in place, it is necessary to evaluate the reliability performance of vertical GaN devices on bulk GaN substrates. The results of high temperature reverse bias (HTRB), high temperature operating life (HTOL), temperature humidity bias (THB), temperature cycling (TC), and inductive avalanche ruggedness tests conducted on vertical GaN devices packaged in standard power packages are reported. It is observed that fundamental failure mechanisms are almost always traced back to the starting substrate material quality, substrate miscut angle, and surface morphology post epi growth. No observation of R-ds drift is made for vertical diodes or transistors fabricated on bulk GaN substrates under the stress conditions mentioned above once a suitable back metal and die attach process is developed. (C) 2015 Elsevier Ltd. All rights reserved.
机译:人们对宽带隙半导体器件非常感兴趣,最近对功率电子应用的垂直GaN结构也很感兴趣。在本文中,讨论了在伪体低缺陷密度(10(4)至10(6)cm(-2))GaN衬底上制造的垂直p-n二极管和垂直结场效应晶体管的初始可靠性研究。 GaN在其本机衬底上的同质外延MOCVD生长以及能够控制GaN漂移层中的掺杂,已实现了垂直器件架构,漂移层厚度为6至40 pm,净载流子电子浓度为2 x 10(15 )至2 x 10(16)cm(-3)。该参数范围适用于需要1200 V至5 kV击穿电压且采用适当边缘终止策略的应用。被测设备演示了功率设备在4.1 kV击穿电压下具有2.8 m Omega-cm(2)的差分比导通电阻(R-sp)的优点。过去几年中,基板质量的提高导致制造了面积达16 mm(2),击穿电压超过1200 V,脉冲电流(100μs)为100-400 A的二极管。此外,由于在天然衬底上生长的高质量晶体,首次在GaN中证明了基于碰撞电离的雪崩击穿。牢牢把握这些关键演示,有必要评估块状GaN衬底上垂直GaN器件的可靠性性能。报告了对标准功率封装中的垂直GaN器件进行的高温反向偏置(HTRB),高温工作寿命(HTOL),温度湿度偏置(THB),温度循环(TC)和电感雪崩强度测试的结果。可以观察到,基本的失效机理几乎总是可以追溯到初始衬底材料的质量,衬底错切角度以及Epi外延后的表面形态。一旦开发了合适​​的背面金属和管芯附着工艺,就无法在上述应力条件下对在块状GaN衬底上制造的垂直二极管或晶体管进行R-ds漂移观察。 (C)2015 Elsevier Ltd.保留所有权利。

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