Improved performance of nanoscale junctionless transistor based on gate engineering approach

摘要

In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (G_m), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.