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Prediction of deformation during manufacturing processes of silicon interposer package with TSVs

机译:具有TSV的硅中介层封装制造过程中的变形预测

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The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during the manufacturing process and to perform a parametric study to minimize the warpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. The Digital Image Correlation (DIC) technique was employed to measure the real-time deformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEA model was established. To reduce the modeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposer were studied. It has been shown that low modulus, low coefficient of thermal expansion (CTE), and high glass transition temperature (T-g) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface. (C) 2016 Elsevier Ltd. All rights reserved.
机译:本文的目的是在制造过程中分析和预测硅穿孔(TSV)中介层封装的热变形,并进行参数研究以最大程度地减少翘曲和热应力。在组装的不同阶段选择样品以观察热行为的变化。数字图像相关(DIC)技术用于测量热负荷下样品的实时变形。为了建立有限元分析(FEA)模型,通过DIC和动态力学分析(DMA)对材料特性进行了表征。根据实验确定的材料特性和变形数据,建立了验证的有限元分析模型。为了减少仿真中的建模复杂性和计算时间,假定C4 /底部填充层,微凸块/底部填充层和TSV中介层是各向同性的。各向同性层的最有效材料性能是通过复合理论计算得出的。此外,仿真遵循顺序制造过程进行,以研究每个步骤的热变形变化并获得更准确的预测结果。仿真的热行为与实验结果吻合良好,该验证的仿真模型用于参数研究。进行了一系列的模拟,以最小化封装翘曲。为避免分层失败,还评估了中介层和底部填充材料之间的界面应力。研究了内插器底部填充材料性能,衬底材料性能,衬底厚度和内插器中TSV密度(Cu体积分数)的影响。结果表明,低模量,低热膨胀系数(CTE)和高玻璃化转变温度(Tg)底部填充,以及低模量和低CTE基板可以缓解封装翘曲和中介层之间界面处的应力发展和底部填充。而且,较大的Cu体积TSV中介层和较厚的基板可以减少封装的翘曲和界面处的应力。 (C)2016 Elsevier Ltd.保留所有权利。

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