A run-time built-in approach of TID test in SRAM based FPGAs

摘要

Run-time TID test in SRAM based FPGAs can improve reliability in space applications, but none feasible approach has been presented. This paper proposes a lightweight built-in test approach, in which the propagation delay of combinational logic in FPGA is measured with ring oscillator in runtime. The differences between propagation delays in different time slots are provided as the metric of TID degradation. The irradiation experiments on Xilinx Zynq chip prove the validity of the proposed method. (C) 2016 Elsevier Ltd. All rights reserved.