Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC

摘要

Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit. (C) 2015 Elsevier Ltd. All rights reserved.