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Integrated modeling of Self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

机译:受限几何结构(FinFET,NWFET和NSHFET)晶体管自热的集成建模及其对20 nm以下现代集成电路可靠性的影响

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The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.
机译:晶体管拓扑结构从平面型晶体管转变为有限型晶体管(例如FinFET,Nanowire FET,Nanosheet FET)已达到20 nm以下集成电路(IC)的理想性能规格,但仅以增加功率密度和散热为代价抵抗性。因此,自热效应(SHE)已成为IC性能/可靠性的关键问题。实际上,温度是确定IC可靠性的最重要因素之一,例如负偏置温度不稳定性(NBTI),热载流子注入(HCI)和电迁移(EM)。因此,准确的SHE模型对于可预测的,具有可靠性的IC设计至关重要。尽管SHE由与IC的各个层相关的热阻/电容共同确定,但大多数研究人员专注于层次结构内的隔离组件(即单个晶体管,少量特定电路配置或专用封装类型)。这种分散的方法使得很难验证SHE对基于受限几何晶体管的IC性能和可靠性的影响。在本文中,我们将理论模型和系统晶体管特性相结合,以提取晶体管级的热参数,从而证明了多重时间恒定热电路对预测现代20 nm以下晶体管的时空SHE的重要性。基于完善的伯克利短通道IGFET模型通用多栅极(BSIM-CMG)模型,我们通过Verilog-A检查了典型数字电路(例如环形振荡器)和模拟电路(例如两级运算放大器)中的SHE基于HSPICE的仿真。同样,我们使用有效的介质近似值对后端(BEOL)互连和IC封装开发了一种用于封装IC的基于物理的热紧凑模型。我们集成了这些组件,以研究SHE行为对IC可靠性的影响,并解释了为什么必须采用各种(仿生)策略来提高自热IC的寿命。

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