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Extended SPICE-like model accounting for layout effects on snapback phenomenon during ESD events.

机译:类似于SPICE的扩展模型,说明了ESD事件期间布局对回跳现象的影响。

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摘要

An extended SPICE-like model for snapback phenomenon including the impact of gate length and substrate on the holding voltage is presented. Substrate conduction is analytically solved thanks to a transmission line model. A fast extraction methodology is also described. This model is in good agreement with the measurements performed on deeply submicron CMOS technologies.
机译:提出了一种扩展的类似于SPICE的回跳现象模型,其中包括栅极长度和衬底对保持电压的影响。借助传输线模型可以解析地解决衬底导电问题。还描述了一种快速提取方法。该模型与在深亚微米CMOS技术上进行的测量非常吻合。

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